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Host Interface (HI08)
Table 6-17. Interface Status Register (ISR) Bit Definitions
Bit Number
7
Bit Name
HREQ
Reset Value
0 (Hardware
and Software
reset)
1 (Individual
reset and
TREQ is set)
1 (Stop reset
and TREQ is
set)
Description
Host Request
If HDRQ is set, the HREQ bit indicates the status of the external transmit
and receive request output signals (HTRQ and HRRQ). If HDRQ is
cleared, HREQ indicates the status of the external host request output
signal (HREQ). The HREQ bit is set from either or both of two
conditions— the receive byte registers are full or the transmit byte
registers are empty. These conditions are indicated by status bits: ISR
RXDF indicates that the receive byte registers are full, and ISR TXDE
indicates that the transmit byte registers are empty. If the interrupt
source is enabled by the associated request enable bit in the ICR, HREQ
is set if one or more of the two enabled interrupt sources is set.
HDRQ
0
0
1
1
HREQ
0
1
0
1
Effect
HREQ is cleared; no host processor
interrupts are requested.
HREQ is set; an interrupt is requested.
HTRQ and HRRQ are cleared, no host
processor interrupts are requested.
HTRQ or HRRQ are set; an interrupt is
requested.
6–5
0
Reserved. Write to 0 for future compatibility.
4
HF3
0
Host Flag 3
Indicates the state of HF3 in the HCR on the DSP side. HF3 can be
changed only by the DSP56311. Hardware and software reset clear
HF3.
3
HF2
0
Host Flag 2
Indicates the state of HF2 in the HCR on the DSP side. HF2 can be
changed only by the DSP56311. Hardware and software reset clear
HF2.
2
TRDY
1
Transmitter Ready
Indicates that TXH:TXM:TXL and the HRX registers are empty. If TRDY
is set, the data that the host processor writes to TXH:TXM:TXL is
immediately transferred to the DSP side of the HI08. This feature has
many applications. For example, if the host processor issues a host
command that causes the DSP56311 to read the HRX, the host
processor can be guaranteed that the data it just transferred to the HI08
is that being received by the DSP56311. Hardware, software, individual,
and stop resets all set TRDY.
CAUTION:
TRDY = TXDE and HRDF
1
TXDE
1
Transmit Data Register Empty
Indicates that the transmit byte registers (TXH:TXM:TXL) are empty and
can be written by the host processor. TXDE is set when the contents of
the transmit byte registers are transferred to the HRX register. TXDE is
cleared when the transmit register (TXL or TXH according to HLEND bit)
is written by the host processor. The host processor can set TXDE using
the initialize function. TXDE can assert the external HTRQ signal if the
TREQ bit is set. Regardless of whether the TXDE interrupt is enabled,
TXDE indicates whether the TX registers are full and data can be latched
in (so that polling techniques may be used by the host processor).
Hardware, software, individual, and stop resets all set TXDE.
DSP56311 User’s Manual, Rev. 2
6-26
Freescale Semiconductor
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